A transistor is used as an amplifier in CB mode with a load resistance of 5 k$\mathrm{\Omega }$. The current gain of the amplifier is 0.98 and the input resistance is 70 $\mathrm{\Omega }$, the voltage gain and power gain respectively are :
(1) 70, 68.6                         

(2) 80, 75.6

(3) 60, 66.6                         

(4) 90, 96.6

In the following circuits PN-junction diodes ${\mathrm{D}}_1$, ${\mathrm{D}}_2$ and ${\mathrm{D}}_3$ are ideal for the following potential of A and B, the correct increasing order of resistance between A and B will be

(i) – 10 V, – 5V           (ii) – 5V, – 10 V
(iii) – 4V, – 12V

(a) (i) < (ii) < (iii)                       (b) (iii) < (ii) < (i)
(c) (ii) = (iii) < (i)                       (d) (i) = (iii) < (ii)

The circuit shown in the following figure contains two diode ${\mathrm{D}}_1$ and ${\mathrm{D}}_2$ each with a forward resistance of 50 ohms and with infinite backward resistance. If the battery voltage is 6 V, the current through the 100 ohm resistance (in amperes) is

1.  Zero 
2.  0.02
3.  0.03 
4.  0.036

The contribution in the total current flowing through a semiconductor due to electrons and holes are $\frac{3}{4}$ and $\frac{1}{4}$ respectively. If the drift velocity of electrons is $\frac{5}{2}$ times that of holes at this temperature, then the ratio of concentration of electrons and holes is
1. 6 : 5                 

2. 5 : 6

3. 3 : 2                 

4. 2 : 3

Ge and Si diodes conduct at 0.3 V and 0.7 V respectively. In the following figure if Ge diode connection are reversed, the valve of ${\mathrm{V}}_0$ changes by 

(1) 0.2 V                   

(2) 0.4 V

(3) 0.6 V                   

(4) 0.8 V

In the following circuit, find ${\mathrm{I}}_1$ and ${\mathrm{I}}_2$.

(a) 0, 0
(b) 5 mA, 5 mA
(c) 5 mA, 0
(d) 0, 5 mA

For the transistor circuit shown below, if $\mathrm{\beta }$ = 100, the voltage drop between emitter and base is 0.7 V, then the value of ${\mathrm{V}}_{\mathrm{CE}}$ will be:
                  
1. 10 V
2. 5 V
3. 13 V
4. 0 V

The following configuration of gate is equivalent to

1. NAND
2. XOR
3. OR
4. None of these

Figure gives a system of logic gates. From the study of truth table it can be found that to produce a high output (1) at R, we must have

(1) X = 0, Y = 1

(2) X = 1, Y = 1

(3) X = 1, Y = 0

(4) X = 0, Y = 0

The combination of gates shown below produces

(1) AND gate

(2) XOR gate

(3) NOR gate

(4) NAND gate