The circuit represents a full wave bridge rectifier when switch \(S\) is open. The output voltage \((\text V_0)\) pattern across \(R_L\) when \(S\) is closed:
1. | 2. | ||
3. | 4. |
1. | Zener voltage remains constant at the breakdown. |
2. | It is designed to operate under reverse bias. |
3. | The depletion region formed is very wide. |
4. | \(\mathrm{p}\) and \(\mathrm{n}\) regions of the Zener diode are heavily doped. |
The output of the logic circuit shown is equivalent to a/an:
1. \(\text{OR}\) gate
2. \(\text{NOR}\) gate
3. \(\text{AND}\) gate
4. \(\text{NAND}\) gate
Two amplifiers of voltage gain 20 each, are cascaded in series. If 0.01 volt a.c. input signal is applied across the first amplifier, the output a.c. signal of the second amplifier in volts is:
1. 2.0
2. 4.0
3. 0.01
4. 0.20
1. | A | B | C | 2. | A | B | C |
0 | 0 | 0 | 0 | 0 | 0 | ||
0 | 1 | 1 | 0 | 1 | 1 | ||
1 | 0 | 0 | 1 | 0 | 1 | ||
1 | 1 | 1 | 1 | 1 | 0 | ||
3. | 0 | 0 | 1 | 4. | 0 | 0 | 1 |
0 | 1 | 0 | 0 | 1 | 0 | ||
1 | 0 | 0 | 1 | 0 | 1 | ||
1 | 1 | 1 | 1 | 1 | 0 |
1. | both circuits (a) and (c) |
2. | circuit (a) only |
3. | circuit (b) only |
4. | circuit (c) only |
1. | decreases for conductors but increases for semiconductors. |
2. | increases for both conductors and semiconductors. |
3. | decreases for both conductors and semiconductors. |
4. | increases for conductors but decreases for semiconductors. |