When the NPN transistor is used as an amplifier:
1. the electrons move from base to collector.
2. the holes move from emitter to base.
3. the electrons move from collector to base.
4. the holes move from collector to emitter.

The emitter-base junction of a transistor is …… biased while the collector-base junction is ……. biased

(1) Reverse, forward                       

(2) Reverse, reverse
(3) Forward, forward                       

(4) Forward, reverse

In an NPN transistor the collector current is 24 mA. If 80% of electrons reach collector its base current in mA is

1. 36                       2. 26
3. 16                       4. 6

If $\mathrm{\alpha }$ = 0.98 and current through emitter ${\mathrm{i}}_{\mathrm{e}}$ = 20 mA, the value of $\mathrm{\beta }$ is 
(a) 4.9                  (b) 49
(c) 96                   (d) 9.6

In an NPN transistor circuit, the collector current is 10 mA. If 90% of the electrons emitted reach the collector, the emitter current (${\mathrm{i}}_{\mathrm{E}}$) and base current (${\mathrm{i}}_{\mathrm{B}}$) are given by 
(1) ${\mathrm{i}}_{\mathrm{E}}$ = –1 mA, ${\mathrm{i}}_{\mathrm{B}}$ = 9 mA
(2) ${\mathrm{i}}_{\mathrm{E}}$ = 9 mA, ${\mathrm{i}}_{\mathrm{B}}$ = – 1 mA
(3) ${\mathrm{i}}_{\mathrm{E}}$ = 1 mA, ${\mathrm{i}}_{\mathrm{B}}$ = 11 mA
(4) ${\mathrm{i}}_{\mathrm{E}}$ = 11 mA, ${\mathrm{i}}_{\mathrm{B}}$ = 1 mA

Least doped region in a transistor 

(1) Either emitter or collector

(2) Base

(3) Emitter

(4) Collector

The transistors provide good power amplification when they are used in 

(1) Common collector configuration

(2) Common emitter configuration

(3) Common base configuration

(4) None of these

The transfer ratio of a transistor is 50. The input resistance of the transistor when used in the common-emitter configuration is 1 k$\mathrm{\Omega }$. The peak value for an A.C input voltage of 0.01 V peak is:

1. 100 μA

2. 0.01 mA

3. 0.25 mA

4. 500 μA

A common emitter amplifier is designed with NPN transistor ($\mathrm{\alpha }$ = 0.99). The input impedance is 1 K$\mathrm{\Omega }$ and load is 10 K$\mathrm{\Omega }$. The voltage gain will be 

(1) 9.9                           

(2) 99
(3) 990                         

(4) 9900

For the given combination of gates, if the logic states of inputs A, B, C are as follows A = B = C = 0 and A = B = 1, C = 0 then the logic states of output D are

(a) 0, 0
(b) 0, 1
(c) 1, 0
(d) 1, 1