Q. No.To get output \(Y = 1\) in the given circuit which of the following input will be correct?
| \(A\) | \(B\) | \(C\) | |
| 1. | 1 | 0 | 1 |
| 2. | 1 | 1 | 0 |
| 3. | 0 | 1 | 0 |
| 4. | 1 | 0 | 0 |
Subtopic: Logic gates |
92%
Level 1: 80%+
AIPMT - 2012
Hints
Given below are two statements:
| Assertion (A): | NAND or NOR gates are called digital building blocks. |
| Reason (R): | The repeated use of NAND (or NOR) gates can produce all the basic or complicated gates. |
| 1. | Both (A) and (R) are True and (R) is the correct explanation of (A). |
| 2. | Both (A) and (R) are True but (R) is not the correct explanation of (A). |
| 3. | (A) is True but (R) is False. |
| 4. | Both (A) and (R) are False. |
Subtopic: Logic gates |
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Level 1: 80%+
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The output of an OR gate is \(1\):
| 1. | if either or both inputs are \(1\). |
| 2. | only if both inputs are \(1\) or zero. |
| 3. | if either input is zero. |
| 4. | if both inputs are zero. |
Subtopic: Logic gates |
89%
Level 1: 80%+
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The given truth table is for which logic gate:
1. NAND
2. XOR
3. NOR
4. OR
| A | B | Y |
| \(1\) | \(1\) | \(0\) |
| \(0\) | \(1\) | \(1\) |
| \(1\) | \(0\) | \(1\) |
| \(0\) | \(0\) | \(1\) |
2. XOR
3. NOR
4. OR
Subtopic: Logic gates |
88%
Level 1: 80%+
AIPMT - 2002
Hints
The final gate in the circuit shown is a \(3\)-input OR-gate, which outputs a low (FALSE) only when all inputs are low (FALSE). A 'low' voltage is considered to be \(0\) or FALSE, while a 'high' voltage is considered to be \(1\) or TRUE.
For a certain input, it is observed that \(Y_1=Y_2=0,Y_3=1.\) Which, of the following inputs, can give this condition?
1. \(A=B=C=0\)
2. \(A=B=C=1\)
3. \(A=1,B=0,C=1\)
4. \(A=0,B=1,C=0\)
For a certain input, it is observed that \(Y_1=Y_2=0,Y_3=1.\) Which, of the following inputs, can give this condition?
1. \(A=B=C=0\)
2. \(A=B=C=1\)
3. \(A=1,B=0,C=1\)
4. \(A=0,B=1,C=0\)
Subtopic: Logic gates |
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Level 1: 80%+
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An input signal to a logic circuit's inputs is represented by a \(0,\) if the voltage is low (true) and by a \(1,\) if the voltage is high (false). The truth table representing the operation of the circuit is given by:
\(\begin{array}{|c|c|c|} \hline A & B & Y~\text{(output)} \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array}\)
An input consisting of the following is presented to the pins \(A\) and \(B\):
The output \(Y\) is:
\(\begin{array}{|c|c|c|} \hline A & B & Y~\text{(output)} \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array}\)
An input consisting of the following is presented to the pins \(A\) and \(B\):
| 1. | pin A: \(0110101001\) |
| 2. | pin B: \(1000011100\) |
| 1. | \(0110100001\) |
| 2. | \(1000010100\) |
| 3. | \(0111100011\) |
| 4. | \(1001010010\) |
Subtopic: Logic gates |
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When the output of an OR gate is applied as input to a NOT gate, then the combination acts as a:
1. NAND gate
2. NOR gate
3. AND gate
4. OR gate
1. NAND gate
2. NOR gate
3. AND gate
4. OR gate
Subtopic: Logic gates |
87%
Level 1: 80%+
NEET - 2024
Hints
An AND gate is followed by a NOT gate in series. With two inputs \(A\) and \(B,\) the Boolean expression for the output \(Y\) will be:
1. \(\overline{{A}{+}{B}}\)
2. \(\overline{A.B}\)
3. \(A.B\)
4. \(\overline{\overline{A}{+}{B}}\)
1. \(\overline{{A}{+}{B}}\)
2. \(\overline{A.B}\)
3. \(A.B\)
4. \(\overline{\overline{A}{+}{B}}\)
Subtopic: Logic gates |
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Consider the logic circuit represented in the above diagram. Assume that all the elements used are ideal.
Suppose that the inputs are as follows:
\(A\) = True, \(B\) = False, \(C\) = True
Which, of the following, is correct?
| 1. | \(X_1\) = True | 2. | \(X_2\) = True |
| 3. | \(X\) = False | 4. | none of the above |
Subtopic: Logic gates |
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Level 1: 80%+
Hints
To get output \('1’\) at \(R, \) for the given logic gate circuit the input values must be:
1. \(X = 0, Y = 1 \)
2. \(X = 1, Y = 1 \)
3. \(X = 1, Y = 0 \)
4. \(X = 0, Y = 0 \)
1. \(X = 0, Y = 1 \)
2. \(X = 1, Y = 1 \)
3. \(X = 1, Y = 0 \)
4. \(X = 0, Y = 0 \)
Subtopic: Logic gates |
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Level 1: 80%+
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